Xanadu Quantum Technologies and ASML have launched a technical collaboration to reduce optical propagation loss in integrated silicon photonic circuits, a key challenge for scalable fault-tolerant quantum computing hardware
Reducing optical loss in silicon photonic circuits has become a central engineering challenge for quantum computing hardware, and now two major players are betting that advanced lithography can shift the limits. Xanadu Quantum Technologies and ASML have announced a research partnership focused on minimizing photon loss in integrated photonic chips-a bottleneck that directly constrains the feasibility of fault-tolerant quantum error correction in photonic quantum processors.
Physical limits in photonic circuits
At the heart of the problem is line edge roughness (LER), a nanometer-scale imperfection that forms along the sidewalls of silicon waveguides during deep-ultraviolet (DUV) and extreme-ultraviolet (EUV) lithography and subsequent etching. Even small deviations in waveguide geometry scatter photons out of the intended optical path, causing Rayleigh scattering and increasing propagation loss. In photonic quantum computing, where each photon can represent a qubit or a resource state, these losses accumulate rapidly across complex routing and interfere with the generation of nonclassical states required for error correction.
For Xanadu, which develops room-temperature photonic quantum processors, the ability to suppress optical loss is not just a matter of efficiency-it determines the physical qubit overhead and the threshold for implementing quantum error correction codes. Lower loss means fewer photons are needed to encode and protect logical qubits, reducing the scale and complexity of the hardware required for practical computation.
Engineering the fabrication process
The collaboration will leverage ASML's advanced exposure systems and computational lithography to optimize the patterning conditions that define waveguide sidewalls. The technical goal is to achieve ultra-smooth sidewalls that minimize LER, thereby reducing Rayleigh scattering and photon loss. This approach targets both the routing circuits and the modules responsible for generating squeezed states, which are essential for continuous-variable quantum error correction schemes.
While the companies have not disclosed specific device metrics or fabrication yields, the focus on process node optimization reflects a broader industry trend: as quantum hardware moves from laboratory prototypes to commercial-scale chips, reproducibility and control over nanofabrication become decisive. Previous efforts in the field have shown that even sub-nanometer improvements in sidewall roughness can translate into measurable reductions in optical loss, but achieving these gains at scale remains a formidable challenge.
Impact on quantum error correction
Reducing optical propagation loss is not a marginal improvement for photonic quantum computing-it is a prerequisite for scaling error-corrected architectures. In continuous-variable photonic systems, higher loss directly increases the number of physical photons required to encode a logical qubit and raises the threshold for photon subtraction, a key operation in error correction protocols. This means that every incremental reduction in loss can have an outsized effect on the resource requirements for building a useful quantum processor.
Industry observers will note that Xanadu's move to deepen its semiconductor ecosystem partnerships comes as other quantum hardware developers are also seeking to address fabrication-induced noise and loss. For context, similar efforts to benchmark and improve quantum hardware in industrial settings have been reported earlier in the context of trapped-ion and neutral-atom systems, where different physical mechanisms set the dominant error sources.
Remaining barriers and outlook
Despite the technical ambition, the collaboration remains at the research stage, with no public data yet on achieved loss rates, device uniformity, or reproducibility across wafers. The transition from laboratory-scale fabrication to commercial foundry processes is rarely straightforward, and improvements in one process parameter can introduce new sources of variability or defect. The absence of peer-reviewed device benchmarks or independent replication means that the practical impact of the partnership will depend on future technical disclosures and, ultimately, on whether the optimized process can deliver low-loss photonic chips at scale.
For now, the Xanadu-ASML partnership signals a recognition that quantum hardware engineering is inseparable from the realities of semiconductor manufacturing. The ability to control nanometer-scale imperfections is not just a matter of technical pride-it is the difference between a laboratory demonstration and a system capable of running error-corrected quantum algorithms. Until reproducible, low-loss photonic chips are demonstrated in hardware, claims of scalable, fault-tolerant photonic quantum computing remain conditional on overcoming these fabrication barriers.
Optical loss in integrated photonic circuits refers to the fraction of photons that are scattered or absorbed as they propagate through waveguides and other optical components. In quantum photonic devices, loss is especially critical because each lost photon can represent a lost qubit or a failed operation, and error correction schemes require extremely low loss to function effectively. Line edge roughness, introduced during lithography and etching, is a dominant source of scattering loss in silicon photonics. Achieving ultra-low-loss waveguides is therefore a foundational requirement for building large-scale, error-corrected photonic quantum processors.
