SEALSQ Corp and its French subsidiary IC'Alps have detailed progress on QASIC, a custom post-quantum ASIC platform aiming to embed quantum-resistant cryptography directly into application-specific silicon for sectors including automotive and healthcare
SEALSQ Corp, a developer of post-quantum semiconductor and digital identity technologies, has provided an engineering update on its QASIC platform, a custom application-specific integrated circuit (ASIC) architecture designed to implement quantum-resistant cryptography at the hardware level. Developed through its French chip design subsidiary IC'Alps, QASIC is intended to address the anticipated vulnerability of classical public-key cryptography to future quantum computers by embedding post-quantum cryptographic (PQC) algorithms directly into customer-specific silicon devices.
QASIC Platform Architecture
The QASIC initiative combines SEALSQ's post-quantum root-of-trust intellectual property with IC'Alps' expertise in analog and mixed-signal ASIC design. The platform is structured to support three main deployment models: catalog PQC integrated circuits for standard security microcontrollers, fully custom ASICs tailored to specific power, latency, and area requirements, and chiplet-based hardware security modules (CHSMs) that integrate pre-certified secure enclaves. The engineering roadmap remains on schedule, with the first functional prototype targeted for delivery in 2026.
Target Sectors and Technical Scope
QASIC is being positioned for use in cybersecurity infrastructure, medical and healthcare devices, and automotive systems. In cybersecurity, the platform is intended for secure microcontrollers, identity authentication engines, and hardware security modules for critical infrastructure. In healthcare, the focus is on implantable and connected diagnostic devices requiring robust data protection. For automotive applications, QASIC aims to support software-defined vehicles, autonomous driving compute units, vehicle-to-everything (V2X) communications, and secure over-the-air updates. The platform leverages RISC-V-based system-on-chip (SoC) architectures, embedded non-volatile memory, and functional safety features compliant with ISO 26262 standards.
Manufacturing and Foundry Integration
IC'Alps manages QASIC production across a global foundry network, including TSMC, GlobalFoundries, STMicroelectronics, Intel Foundry, X-FAB, and ams-OSRAM. This approach is intended to ensure supply chain resilience and compatibility with established semiconductor manufacturing processes. The platform's design flow incorporates ultra-low power analog and mixed-signal techniques, as well as reusable intellectual property blocks for rapid customization. Certification and production are planned to align with sector-specific regulatory requirements, particularly in automotive and medical markets.
Engineering Milestones and Remaining Challenges
According to SEALSQ, the QASIC engineering track is on pace to deliver a functional prototype by 2026, but the company has not yet released detailed performance metrics or independent benchmarking data. The integration of hardware-accelerated PQC into ASICs remains a complex engineering challenge, particularly in balancing power consumption, latency, and silicon area with the computational demands of post-quantum algorithms. The platform's reliance on a global foundry ecosystem introduces additional variables in process variation and supply chain management. As with other post-quantum hardware initiatives, the practical security and performance of QASIC-based devices will depend on the maturity of PQC standards and the ability to validate implementations against evolving cryptanalytic techniques. For context on recent advances in quantum-resistant hardware, readers may be interested in a report on new quantum LDPC code designs for logical qubit density, available here.
Post-quantum cryptography refers to cryptographic algorithms designed to remain secure against attacks from large-scale quantum computers, which are expected to break widely used public-key schemes such as RSA and elliptic-curve cryptography. Unlike quantum key distribution, which relies on quantum communication channels, post-quantum algorithms are implemented on conventional hardware but require significant computational resources. Embedding PQC directly into ASICs can reduce attack surfaces and improve performance, but also introduces new engineering and validation challenges. The transition to post-quantum security is expected to be gradual, with hybrid systems and ongoing evaluation of algorithmic resilience as quantum hardware capabilities advance.
