A proposed modular code links 72-qubit and 116-qubit planar modules across sparse seams. Circuit-level simulations tested whether logical errors stay low when those links are noisier than on-chip gates
In circuit-level simulations, a modular quantum error-correction design maintained low logical error rates even when its inter-chip links were assigned ten times the error rate of on-chip gates. That is a demanding test for an architecture whose code depends on checks crossing the boundaries between small chips. The result is computational evidence, not a demonstration on connected quantum hardware.
Flat modules
Researchers at Google Quantum AI and Google DeepMind collaborated with MIT on the design, described in the arXiv manuscript Low-Overhead Quantum Error Correction with Boundary-Connected Planar Modules. It arranges small, flat Euclidean chips in a hyperbolic tiling, allowing the combined system to support a high-rate quantum low-density parity-check (qLDPC) code without long-range wire crossings within each chip. The approach targets a central engineering challenge for qLDPC codes: obtaining their high encoding rates while keeping each module's layout planar and locally connected.
The architecture starts by dividing a closed hyperbolic surface into flat lattice patches with side length L. Each patch becomes a module containing either 72 or 116 qubits. Sparse, static couplers along module boundaries connect neighboring patches, and stabilizers that span a seam are measured using cat-flagged syndrome-extraction circuits designed to detect errors introduced during the checks.
Testing noisy seams
The team modeled circuit-level noise with the SI1000 model, setting the physical error probability to 0.1% and the seam error probability to 1%. Decoding used the AlphaQubit neural network alongside correlated minimum-weight perfect matching (MWPM). In these simulations, the design retained low logical error rates despite seam errors being ten times higher than on-chip gate errors. The manuscript reports more than a 30-fold reduction in physical-qubit overhead relative to standard two-dimensional surface codes.
That comparison concerns the code architecture and its modeled resource requirements; it is not a reduction already demonstrated on a processor. The numerical result applies to the stated noise model and decoder setup, including the assumed 1% seam error rate.
Gates across tiles
The proposal also addresses logical operations. Fault-tolerant walking circuits use code automorphisms-global permutations of the tiling-to implement logical gates. Modular ribbon extractors provide another route: a closed loop of ancillas attached along module boundaries, described as about 4.5 times smaller than the memory itself. The authors present these methods as ways to support universal fault-tolerant logic without a proportional increase in spatial overhead.
The work remains at the circuit-simulation stage rather than demonstrating a code running across physically connected chips. Earlier work on surface-code decoding examined offline reweighting of recorded stabilizer measurements; this manuscript instead changes the code layout and the connections between modules.
From model to hardware
Connecting small chips could ease the need to route long-range wires across a single planar device, while placing additional demands on the boundaries. Those links must support reliable syndrome measurements, and the simulations model their errors as higher than those of on-chip gates. The architecture uses predetermined sparse couplers rather than a fully programmable network of long-distance connections.
Quantum error correction encodes logical information across multiple physical qubits and uses measured stabilizers to detect error patterns without directly reading out the encoded state. A decoder interprets those measurement outcomes and identifies likely errors. The proposed modules combine that familiar error-correction process with a hyperbolic global layout, aiming to reduce physical-qubit overhead while keeping individual chips flat and compact.
