Open AI Agents Cut QEC Decoder Inference Costs 11.5-Fold

IBM Research reported on October 13, 2026, that an automated agent search produced a proposed hardware design for quantum error correction (QEC) with up to 204 times the speed of a baseline implementation. The work targets the classical processing that decodes error information gathered during quantum operations. IBM's hardware figures come from high-level synthesis (HLS), not testing of a fabricated chip.

Agents reshape decoder code

The study applies an Agent Factory to C++ implementations of Relay-BP, a decoding algorithm for the Gross [[144,12,12]] bivariate bicycle qLDPC code. Relay-BP processes syndrome measurements-the information used to estimate quantum errors and determine corrections. A decoder must process these data fast enough to keep pace with repeated measurement and correction cycles in fault-tolerant computing.

High-rate quantum low-density parity-check codes can reduce physical-to-logical qubit overhead compared with standard 2D surface codes. Their dense, non-local check matrices also make decoding a demanding classical-hardware problem, particularly when calculations need to run in parallel. Earlier IBM qLDPC work reported a simulation in which 12 logical qubits were stored for nearly one million rounds using 288 physical qubits, at a physical error rate of about 0.1%; that result concerned code behavior in simulation, not a fabricated decoder chip.

The framework pairs a coordinator model with four parallel worker agents. The workers propose code and architecture changes, which are checked for correctness and evaluated through synthesis. Described transformations include organizing memory by checks, turning loop reductions into compile-time recursive trees, and maintaining message data in two layouts. The target is Initiation Interval II = 1, a scheduling measure for starting a new loop iteration every cycle. Ruchir Puri, an IBM Fellow and chief scientist at IBM Research, described the approach as a coordinated exploration in which a coordinator directs parallel workers to develop and synthesize alternatives within a set search budget.

This design problem is related to the decoder demands behind earlier QEC work, though that report concerned scheduling logical operations rather than designing decoder hardware. IBM's technical account of the agent factory describes the hardware-design experiment and its inference infrastructure.

Speed and serving costs

IBM compared proprietary, fully open, and hybrid agent configurations, each with a budget of 100 design hypotheses. The proprietary-model run reached the highest reported result: a 204-fold estimated hardware speedup at an inference cost of about $299. The fully open configuration achieved a 52-fold estimated speedup for about $26 in inference, an approximately 11.5-fold reduction in inference cost relative to the proprietary run. The figures represent separate search runs, not measurements from a manufactured device.

For the open configuration, IBM ran open-weight models on premises using the llm-d distributed inference stack. IBM reported a prefix-cache hit rate of about 98% and a blended serving cost of roughly $0.11 per million tokens. Reusing prompt prefixes reduced repeated inference work during the search. These are model-serving and search costs, not estimates of manufacturing a future decoder chip.

The cost comparison matters because an agent-based design search can involve many model calls. The reported $26 covers inference for the stated all-open search; it is not the broader engineering cost of turning a proposed design into a reliable device. The reported comparison also reflects the individual runs and their fixed hypothesis budget.

What the results establish

HLS translates a high-level hardware description, such as C++ code, into a proposed hardware architecture. It allows designers to explore how changes to memory access or loop structure may affect a circuit's estimated performance. In this case, the agents optimized an HLS C++ description of a classical decoder; they did not build or operate a quantum processor.

The reported 204-fold and 52-fold speedups are synthesis-based estimates relative to a baseline, not measured performance from an ASIC or FPGA. No chip was fabricated and tested as part of the reported experiment. The results therefore describe automated exploration of decoder architectures, rather than a validated commercial chip or a decoder demonstrated in a running fault-tolerant quantum system.

In HLS, an initiation interval of one means the design is scheduled to begin a new loop iteration every clock cycle. It does not by itself specify clock frequency, the time needed to complete a decoding task, or the performance of fabricated hardware. Those measurements belong to subsequent implementation and testing on a target platform.