Rigetti Computing has reorganized its operations, creating a dedicated Systems Delivery group to manage manufacturing and deployment of superconducting quantum hardware, while consolidating processor R&D into a separate technology division
Rigetti Computing, a developer of superconducting quantum processors, has restructured its internal organization to separate the engineering and deployment of commercial quantum systems from its core quantum processor research and development. The company has established a new Systems Delivery group responsible for manufacturing, customer-facing engineering, and commercial system integration, while consolidating all hardware engineering and chiplet development within a streamlined Technology division. This move is intended to allow the processor R&D team to focus on improving device fidelity and advancing the hardware roadmap, while the delivery group manages the practical challenges of scaling and deploying quantum systems at customer sites.
System Delivery and Deployment
Historically, Rigetti's core engineering team handled both the development of quantum processors and the logistics of customer installations and field support. The new Systems Delivery organization will now oversee the manufacturing pipeline, commercial sales, and the technical aspects of deploying hardware ranging from the 9-qubit Novera QPU to larger 36-qubit and 108-qubit Cepheus-class systems. This includes managing the assembly, testing, and delivery schedules for on-premises installations at national laboratories and quantum computing centers. The company's integrated manufacturing facility, Fab-1 in Berkeley, California, will now report directly to the Systems Delivery group, aiming to streamline the transition from device fabrication to operational deployment.
Processor Architecture and Performance Targets
Rigetti's Technology division remains focused on advancing the performance of its superconducting quantum processors. The current flagship, the Cepheus-1-108Q, is constructed by tiling twelve 9-qubit chiplets using inter-module couplers to achieve a 108-qubit quantum processing unit (QPU). The company has set a benchmark target of 99.5% median two-qubit controlled-Z (CZ) gate fidelity for this platform. Achieving high-fidelity two-qubit gates across a large, modular architecture remains a central technical challenge, as crosstalk, calibration drift, and fabrication variability can degrade performance as system size increases. The company has not yet reported independent verification of these performance targets, and it remains to be seen how consistently high fidelities can be maintained across all modules in a deployed system.
Manufacturing and Engineering Constraints
Scaling up superconducting quantum hardware from laboratory prototypes to deployable systems requires addressing a range of engineering bottlenecks. These include device yield, wiring complexity, cryogenic integration, and the reproducibility of chiplet-to-chiplet coupling. The integration of Fab-1 manufacturing with the Systems Delivery group is intended to improve coordination between fabrication, assembly, and field deployment, but the practical impact will depend on the ability to maintain device quality and calibration stability at scale. Similar challenges have been encountered by other quantum hardware developers, as seen in efforts to standardize modular architectures for enterprise and research use-such as the manufacturing collaborations described in recent work on scalable trapped-ion systems.
Distinguishing Research From Commercialization
The organizational split reflects a broader trend in the quantum industry, where companies are seeking to separate the demands of research-driven processor development from the operational requirements of delivering and supporting commercial systems. While Rigetti's roadmap includes ambitious targets for system size and gate fidelity, the gap between laboratory benchmarks and reliable field performance remains significant. Achieving reproducible, high-fidelity operation across large, modular superconducting processors will require continued advances in fabrication, calibration, and error mitigation, as well as transparent reporting of system-level performance in real-world deployments.
Gate fidelity is a key metric for evaluating the performance of quantum processors. It measures how closely a physical quantum gate operation matches the ideal mathematical transformation, with higher fidelity indicating fewer errors. In superconducting systems, two-qubit gate fidelity is often limited by crosstalk, decoherence, and calibration drift. Achieving high median gate fidelity across all qubits in a large processor is essential for running deeper quantum circuits and for the eventual implementation of quantum error correction. However, reported fidelities typically reflect best-case or median values under controlled conditions, and maintaining these levels in deployed, multi-module systems remains a major engineering challenge.
