Fujitsu and Yaqumo have begun experimental validation of the STAR architecture on cold-atom quantum processors, aiming to reduce physical qubit overhead and test error correction strategies on hardware using ytterbium atom arrays
Fujitsu Limited and Yaqumo Inc. have moved beyond theoretical proposals and are now running live hardware tests to determine whether the STAR (Space-Time efficient Analog Rotation) architecture can reduce the physical qubit requirements for quantum error correction on neutral-atom quantum processors. This marks a shift from simulation to direct experimental benchmarking, with the companies targeting early-stage fault-tolerant quantum computing platforms that could eventually support hundreds of qubits.
Neutral Atom Hardware in Focus
The experimental platform centers on arrays of cold ytterbium (Yb) atoms, each held and manipulated by optical tweezers and laser-driven gates. Neutral-atom systems offer all-to-all connectivity and flexible qubit arrangement, which are attractive for implementing complex gate operations and error-correcting codes. The STAR architecture, originally designed for superconducting qubits, is being adapted to this platform to minimize the spatial and hardware overhead typically required for arbitrary-angle phase rotations-an essential component for many quantum algorithms and error-correction routines.
Yaqumo's roadmap aims for a neutral-atom quantum processing unit (QPU) with several hundred physical qubits and active quantum error correction by fiscal year 2027. The company's hardware development is supported by industrial partners and investors, including Toyota Motor Corporation and JIC Venture Growth Investments, and leverages supply-chain alliances with SCREEN Holdings, Hamamatsu Photonics, and NKT Photonics.
Software Integration and Control
To bridge the gap between high-level quantum algorithms and the physical hardware, Fujitsu's open-source Open Quantum Toolchain for Operators and Users is being adapted to interface directly with Yaqumo's control stack. This middleware translates quantum circuits into device-level commands, manages job queues, monitors device status, and calibrates pulse sequences for the neutral-atom array. The integration is designed to allow external users to submit quantum programs through a unified cloud API, regardless of the underlying hardware modality, without rewriting their code for each device type.
Key technical goals include reducing the number of physical qubits needed for error-corrected logical operations, supporting arbitrary gate sets, and enabling cloud-based execution and monitoring. The companies report that live circuit benchmarks began in August 2026, following earlier theoretical compatibility studies. The target is to demonstrate hardware and algorithmic benchmarks for early fault-tolerant quantum computing within the next year.
Benchmarking and Engineering Challenges
While the STAR architecture promises to lower the physical qubit overhead for certain gate operations, the practical impact depends on the fidelity of gate implementation, the stability of optical trapping, and the reliability of device calibration. Neutral-atom arrays are susceptible to noise sources such as laser intensity fluctuations, atom loss, and crosstalk between neighboring sites. Achieving high-fidelity arbitrary-angle rotations and maintaining coherence across large arrays remain open engineering challenges.
According to the companies, the current integration stack includes unified device calibration and monitoring, with a focus on supporting hundreds of qubits and quantum error correction benchmarks by fiscal year 2027. However, no independent peer-reviewed results or detailed performance metrics have been released. The collaboration's approach echoes recent efforts in the field to combine hardware advances with software-layer optimization, as seen in reported earlier work on neutral-atom quantum simulation.
Roadmap Versus Demonstrated Capability
Despite the ambitious targets, the transition from laboratory demonstration to a scalable, fault-tolerant quantum computer remains a formidable task. The companies' public roadmap projects several hundred physical qubits with active error correction within a year, but the actual demonstration of logical qubits, sustained error correction cycles, and algorithmic benchmarks on hardware is still pending. The integration of STAR compilation with neutral-atom hardware is a technically plausible route to reducing overhead, but its effectiveness will ultimately depend on the achieved gate fidelities, error rates, and system stability under real experimental conditions.
Without independently verified benchmarks or peer-reviewed publications, the current status should be viewed as an early-stage engineering integration rather than a completed demonstration of fault-tolerant quantum computing. The collaboration's willingness to test architectural ideas on hardware is a positive step, but the field will require transparent reporting of error rates, logical qubit performance, and reproducibility before claims of practical fault tolerance can be substantiated.
Quantum error correction is the process of encoding logical qubits across multiple physical qubits to detect and correct errors arising from noise, decoherence, and imperfect gate operations. In practice, this requires not only high-fidelity gates and measurements but also robust calibration, stable device operation, and efficient decoding algorithms. The overhead-the number of physical qubits required per logical qubit-depends on the error-correcting code, the physical error rates, and the architecture's ability to implement the necessary gate set. Reducing this overhead is a central challenge for building scalable quantum computers, and architectural innovations like STAR are being explored to make error correction more practical on emerging hardware platforms.
