A new government-funded project led by Hitachi aims to move silicon spin-qubit quantum processors from laboratory prototypes toward manufacturable hardware, using Intel's advanced foundry and AIST's research infrastructure
Japan's New Energy and Industrial Technology Development Organization (NEDO) has selected Hitachi, Ltd. to lead a multi-year initiative focused on scaling silicon spin-qubit quantum processors from academic research to industrial fabrication. The project, titled "Accelerating the Development and Demonstration of Next-Generation Quantum Computers to Solve Social Challenges," is scheduled to run through March 2029 and brings together Hitachi, Intel K.K., and the National Institute of Advanced Industrial Science and Technology (AIST). The central objective is to address the engineering and reproducibility challenges that currently limit silicon-based quantum devices to small-scale laboratory demonstrations.
Silicon spin qubits are quantum bits encoded in the spin state of single electrons confined within semiconductor quantum dots. These devices are attractive for quantum computing because they can, in principle, be fabricated using established semiconductor manufacturing processes, including extreme-ultraviolet (EUV) lithography. However, moving from a handful of laboratory qubits to large-scale, fault-tolerant quantum processors requires overcoming significant device-to-device variability, wiring complexity, and thermal management issues at cryogenic temperatures.
Manufacturing and Integration Challenges
The project will use Intel's 18A process technology and a dedicated Process Design Kit (PDK) for quantum devices to design and fabricate silicon spin-qubit chips with more than 100 physical qubits per processor. The use of a commercial foundry process is intended to reduce device variability and improve yield, but the practical impact on qubit coherence, gate fidelity, and reproducibility remains to be demonstrated. Specialized low-power cryogenic packaging and control electronics are also under development to minimize the number of control wires and reduce heat load inside dilution refrigerators, which are required to maintain operating temperatures below 100 millikelvin.
To address the wiring and integration bottleneck, the project includes the development of three-dimensional (3D) high-density packaging techniques. These are designed to connect control electronics and qubit chips at fine pitches, supporting the eventual goal of scaling to arrays of 1,000 or more physical qubits. The roadmap anticipates a prototype 100-qubit silicon quantum processor implementing quantum error-correcting codes by fiscal year 2028, with a 1,000-qubit 3D-integrated platform targeted for 2030. However, these are projected milestones and depend on overcoming substantial engineering and fabrication challenges.
Cloud Access and Research Infrastructure
The initiative will leverage AIST's Global Research and Development Center for Business by Quantum-AI Technology (G-QuAT) to provide a cloud-accessible research environment. This platform is intended to allow external researchers and software developers to run experimental workloads on silicon spin-qubit testbeds, beginning with a planned launch in fiscal year 2027. The integration of cloud-based access is expected to accelerate software and algorithm development, but the practical utility of such testbeds will depend on the stability, calibration, and reproducibility of the underlying hardware.
According to the project announcement, the collaboration builds on Hitachi's prior involvement in Japan's Cabinet Office Moonshot R &D Program (Goal 6) and joint research with RIKEN and imec. By combining Intel's foundry capabilities with AIST's hybrid supercomputing infrastructure, the project aims to create a fabrication and research ecosystem for silicon quantum hardware. However, the transition from laboratory-scale devices to manufacturable, error-corrected quantum processors remains an open engineering problem, and no independent performance data for the proposed hardware has yet been released.
Technical Milestones and Remaining Barriers
The project's technical roadmap includes three main milestones: the launch of a cloud-based experimental service in 2027, delivery of a prototype 100-qubit silicon quantum processor with quantum error correction in 2028, and realization of a 1,000-qubit 3D-integrated platform by 2030. These targets are ambitious and depend on advances in device yield, coherence, gate fidelity, error correction, and cryogenic integration. At present, silicon spin-qubit devices typically operate at temperatures below 100 millikelvin, with coherence times and gate fidelities that vary significantly between devices and fabrication runs. Achieving reproducible, high-yield fabrication at the scale required for fault-tolerant quantum computing remains a central challenge.
For context, the project's use of Intel's 18A process is notable because it represents one of the most advanced commercial semiconductor manufacturing nodes, with feature sizes below 2 nanometers. However, the impact of such advanced lithography on quantum device performance is not yet fully understood, and the transition from laboratory to foundry-scale fabrication introduces new sources of variability and noise. The project's success will depend on whether these engineering challenges can be addressed without sacrificing the quantum coherence and control required for practical computation.
Silicon spin qubits are quantum bits realized by confining single electrons in semiconductor quantum dots and manipulating their spin states using electrical or magnetic fields. These qubits are attractive because they can, in principle, be fabricated using the same processes as conventional silicon transistors, potentially enabling large-scale integration. However, each physical qubit is sensitive to charge noise, interface disorder, and fabrication imperfections, which can degrade coherence and gate fidelity. Quantum error correction is a set of techniques that encodes logical qubits across multiple physical qubits to detect and correct errors, but implementing these codes at scale requires high device yield, stable operation, and low error rates across large arrays. The distinction between physical and logical qubits is central: while physical qubits are the building blocks, only logical qubits protected by error correction can support reliable quantum computation at scale.
