Diraq has opened a new engineering facility in Santa Monica, California, focused on silicon spin-qubit processor development using commercial CMOS foundry processes, as part of its trans-Pacific quantum computing infrastructure
Diraq, a developer of silicon-based quantum computing hardware, has launched a new engineering hub in Santa Monica, California, expanding its US presence with a team dedicated to integrated circuit design, cryogenic CMOS architecture, device modeling, and machine learning for quantum processors. The Santa Monica site joins Diraq's existing US operations in Palo Alto and Chicago, forming a three-node network intended to accelerate the development and testing of CMOS-compatible silicon spin-qubit devices.
Silicon Spin Qubits and CMOS Integration
The core of Diraq's approach is the fabrication of spin qubits in silicon using standard commercial complementary metal-oxide-semiconductor (CMOS) foundry processes. This strategy aims to leverage the scale and reproducibility of established semiconductor manufacturing, integrating both qubit arrays and cryogenic control electronics on a single silicon die. By embedding cryogenic CMOS circuits for qubit drive, readout, and multiplexing directly onto the substrate, Diraq seeks to reduce the wiring complexity and thermal load that typically limit the scaling of quantum processors operating at millikelvin temperatures.
Unlike architectures that require custom materials or exotic fabrication steps, silicon spin qubits are compatible with the same industrial processes used for classical microprocessors. This compatibility is intended to support higher device yield and facilitate the integration of millions of qubits, though the practical challenges of error rates, calibration, and device variability remain significant. Diraq's roadmap targets a commercial product launch by 2029, but the transition from laboratory demonstration to fault-tolerant, large-scale quantum computing will require advances in both device performance and system engineering.
Trans-Pacific Engineering and Testing Network
The Santa Monica engineering hub is part of a broader trans-Pacific infrastructure stack that includes Diraq's Sydney headquarters and R&D center, a device fabrication and physics research facility, and a measurement laboratory in Chicago equipped for cryogenic qubit testing and verification. The Palo Alto office serves as the company's US commercial headquarters, focusing on semiconductor foundry partnerships and integration with the Silicon Valley ecosystem. The Santa Monica team is tasked with multi-disciplinary engineering, including IC architecture, software stack development, cryogenic control electronics, and automated calibration algorithms.
According to Diraq, the Santa Monica facility launched with a 20-person engineering team and plans to double its headcount within a year. The company's distributed model is designed to support rapid iteration between device design, fabrication, and measurement, with engineering and testing nodes in both the US and Australia. This approach reflects a growing trend among quantum hardware developers to establish geographically distributed teams and infrastructure, aiming to combine local talent pools with global manufacturing and research capabilities.
Engineering Challenges and Industry Context
Scaling silicon spin-qubit processors to the million-qubit regime will require not only advances in device fabrication and control electronics but also robust error correction, high-fidelity gate operations, and reliable cryogenic integration. While the use of commercial CMOS foundries offers a potential path to large-scale integration, the physical error rates of spin qubits, the complexity of calibration, and the need for automated device tuning remain open engineering challenges. The company's expansion into Southern California is partly motivated by the region's concentration of semiconductor, aerospace, and defense engineering expertise.
Recent developments in the quantum computing sector have seen a range of hardware platforms-superconducting circuits, trapped ions, neutral atoms, and photonic systems-competing to demonstrate scalable architectures and practical utility. For example, Japan's Institute for Molecular Science recently deployed a neutral-atom quantum computer with a 50-qubit platform, as reported in Science Report's coverage of Shunkai. Each platform faces distinct engineering and physical constraints, and the long-term viability of silicon spin qubits will depend on sustained progress in device reproducibility, error mitigation, and system integration.
Roadmap and Remaining Uncertainties
Diraq's stated goal is to deliver a commercial silicon spin-qubit processor by 2029, leveraging its trans-Pacific engineering and testing infrastructure. However, the company has not yet published peer-reviewed data on large-scale device performance, logical qubit operation, or error-corrected computation. The practical realization of fault-tolerant quantum computing in silicon will require not only high-yield fabrication and low error rates but also scalable calibration, robust cryogenic operation, and integration with classical control systems. As with other quantum hardware roadmaps, the timeline remains subject to technical risk and the pace of engineering progress.
While the expansion of Diraq's US engineering footprint reflects growing investment in quantum infrastructure, the field as a whole continues to grapple with the gap between laboratory prototypes and deployable, useful quantum computers. Independent benchmarking, reproducibility, and transparent reporting of device performance will be essential for evaluating the true scalability and utility of silicon spin-qubit architectures.
Silicon spin qubits are quantum bits realized by controlling the spin state of single electrons confined in semiconductor quantum dots. Their compatibility with CMOS fabrication processes makes them attractive for large-scale integration, but achieving low error rates and stable operation at cryogenic temperatures remains challenging. Unlike logical qubits, which use error correction to protect information, physical spin qubits are directly susceptible to noise and decoherence. The distinction between physical and logical qubits is central to understanding the engineering hurdles that must be overcome before silicon-based quantum processors can perform useful, fault-tolerant computation.
