DARPA has moved Atom Computing, Diraq, IBM and IonQ into the final stage of its quantum benchmarking program, where physical systems, control infrastructure, software and error-correction components will face direct testing rather than plan reviews.
DARPA is moving four competing quantum architectures from paperwork to hardware. Atom Computing, Diraq, IBM and IonQ have been selected for Stage C of the Quantum Benchmarking Initiative, the program's final verification phase, where physical processors, control systems, packaging, software stacks and decoders will undergo direct testing.
Stage C changes the nature of the evaluation. DARPA's Independent Verification and Validation team will measure systems rather than simply audit their research plans, risk models or prototype evidence. The tests will cover four different physical approaches: neutral atoms, silicon spin qubits, superconducting transmons and trapped ions. IBM describes this phase as the point at which assessment moves from conceptual roadmaps to measurements of processors, control systems, cryogenic infrastructure, software and error-correction decoders.
QBI began in 2024 as an expansion of the Underexplored Systems for Utility-Scale Quantum Computing program. Its target is not a raw qubit-count record. DARPA defines utility scale as the point at which a quantum system produces computational value greater than its total capital and operating costs, with the assessment aimed at possible operation by 2033.
The new cohort joins Microsoft and PsiQuantum, which were initial US2QC participants already advancing through Stage C verification. That distinction matters because a roadmap can describe an intended machine while physical verification tests whether the architecture can control and measure the required hardware.
Atom Computing will be assessed through neutral-atom arrays held in optical tweezers. The planned testing includes systems with more than 1,200 physical atoms and will examine two-qubit gate fidelity, mid-circuit measurement and execution of quantum error correction below the relevant error threshold. Microsoft is providing algorithmic support and error-correction codes for the platform. The supplied information identifies planned capabilities but does not establish that a complete fault-tolerant computer has already been demonstrated.
Diraq's route uses silicon spin qubits fabricated on 300-millimeter silicon-on-insulator wafers through CMOS foundry processes. Its stated scaling path runs from an eight-qubit commercial data-center deployment with Equinix in Sydney to 150,000 physical qubits by 2029 and more than two million physical qubits on one die by 2031. A $38 million CHIPS Act Letter of Intent supports onshore manufacturing. Those figures are roadmap targets rather than Stage C measurements of a finished system.
Reaching Stage C gives Diraq access to potential funding of up to $300 million, estimated by Capital Brief at about A$430 million. The company is expected to provide a sequence of technical demonstrations, system updates and design materials. Founder and chief executive Andrew Dzurak has described the transition as an important independent test of whether Diraq's path toward utility-scale quantum computing can withstand rigorous technical scrutiny.
IBM's evaluation will focus on the planned 2029 Quantum Starling architecture. DARPA will examine meter-scale quantum interconnects, modular cryostats operating below 15 millikelvin and FPGA-based real-time error-correction decoders integrated with Qiskit. The relevant question is whether these components work together at system level, not whether any single component can operate in isolation.
IonQ will put successive Superion platforms through testing through 2029, including the Superion 256 architecture. IonQ says DARPA will compare hardware and software performance against the company's technical roadmap rather than evaluate only one generation. The proposed evaluation includes two-qubit gate fidelities of 99.99 percent, reconfigurable optical shuttling networks and manufacturing economics intended to support higher-volume deployment. A two-qubit fidelity figure alone cannot establish long-circuit reliability because leakage, calibration drift, connectivity and decoder performance also affect computation.
The Stage C program will inspect physical QPUs alongside the infrastructure that makes them usable: control electronics, cryogenic packaging and software decoders. That full-stack scope is important. Physical qubits are individual quantum systems, while logical qubits encode information across multiple physical components so errors can be detected or corrected. Increasing the first number does not automatically increase the second.
The numerical targets reveal the breadth of the comparison. Atom Computing's roadmap involves more than 1,200 physical neutral-atom positions; Diraq describes 300-millimeter wafer fabrication and projected counts of 150,000 and more than two million physical qubits; IBM's proposed cryogenic environment is below 15 millikelvin; IonQ identifies a 99.99 percent two-qubit gate-fidelity target. These numbers belong to different architectures and measurement contexts, so they cannot be ranked as though they were one common performance scale.
Stage C therefore has a more demanding test than checking whether a processor can execute a short circuit. It must connect gate operations with measurement, error correction, packaging, cooling and decoding. For the neutral-atom system that includes mid-circuit measurement. For IBM it includes real-time decoding and cryogenic interconnects. For Diraq it includes the manufacturing path from foundry-fabricated chips to much larger arrays. For IonQ it includes transport and volume economics.
The supplied announcement does not provide independent Stage C results, logical error rates, code distances, coherence times, circuit depths, readout fidelities or completed fault-tolerant algorithms for these four companies. Nor does it report an independent reproduction of the projected 2029 or 2031 milestones. Those absences prevent a comparison of achieved computational performance today.
In quantum-information research, the distinction between physical and logical performance is as important as the distinction between component tests and full-system tests in large facilities such as CERN or NASA missions. A reported gate fidelity is a local metric; utility-scale operation requires evidence that errors remain manageable as circuits, devices and supporting infrastructure grow.
QBI's practical standard is more useful than a contest based only on qubit totals because it forces architecture and economics into the same assessment. A system needs high-quality operations, stable calibration, manageable wiring, suitable cooling or optical infrastructure, effective readout and decoding, and a manufacturing process that can reproduce devices. A large projected count cannot substitute for evidence that those requirements can be met together.
That is why Stage C represents a meaningful change even before any final result is reported. DARPA is asking whether the physical systems can support the engineering chain required for fault-tolerant operation. The announcement identifies the test subjects and the intended measurements, but it does not say that any performer has crossed the utility threshold.
The program's evaluation logic is consistent with the engineering emphasis in an earlier fault-tolerance analysis that focused on the physical resources required to turn logical circuits into hardware plans. Here the emphasis shifts from estimating those resources to checking whether commercial architectures can deliver them in physical systems.
The independent scope described by DARPA is also closer to the reproducibility standards associated with peer-reviewed work in Nature and with systems research at MIT than to a single headline benchmark. Such comparisons require clearly defined observables, repeatable operating conditions and separation between projected targets and measured results; Stage C is intended to establish that distinction across hardware and software layers.
Physical and logical qubits should not be treated as interchangeable units. A physical qubit is one controlled device or quantum system; a logical qubit is an encoded degree of freedom distributed across several physical qubits. Error correction measures syndromes and uses a decoder to infer likely errors, but a single correction component or a roadmap for more qubits does not amount to a complete fault-tolerant machine.
The four selections make Stage C the clearest test yet in this program of whether quantum hardware claims can survive contact with system-level measurement. DARPA has not announced utility-scale operation or independent success for any of the new performers. The evidence now supports a narrower but important conclusion: the industry's competing architectures are being placed under the kind of physical scrutiny required to separate ambitious scaling plans from demonstrable engineering progress.
IonQ's announcement details the planned multi-generation comparison in its Stage C program update, while IBM's description of the phase underscores that the measurements extend beyond the processor itself. The eventual significance of the program will depend on the independent results, not on the selection announcement alone.
