D-Wave is giving selected companies and research centers access to a 21-qubit simulator that models photon-loss erasures and real-time error detection before general availability
D-Wave has opened a beta program for a gate-model quantum simulator that can emulate up to 21 qubits while exposing users to the error processes its proposed hardware architecture is designed to detect. Announced on October 1, 2026, the program is an early-access release for selected commercial and research organizations, not a general public launch. The system is not a physical quantum processor and does not demonstrate a useful quantum advantage. Its value lies in letting developers test error-aware circuits before broader software access and future hardware deployments.
For D-Wave, the simulator represents a new stage beyond its production annealing systems: the company is developing a dual-rail superconducting gate-model pathway while continuing to operate its annealing platform. Independent reporting says D-Wave plans to demonstrate further gate-model progress alongside current annealing results and intends to deliver its first dual-rail gate-model machine later in 2026 from a new research center in New Haven, Connecticut. These milestones describe a development roadmap, not an already demonstrated fault-tolerant computer.
The simulator offers an Ideal Mode for rapid algorithm construction and validation, plus a Hardware Emulation Mode. The latter uses a Monte Carlo engine to model stochastic system dynamics and the control flow required when errors are detected during a circuit. That distinction matters: an ideal circuit can show whether an algorithm is logically formulated, while hardware emulation tests how the same design behaves when loss and classical feedback intervene.
Users can program the environment through D-Wave's Ocean software development kit, its Quantum Circuit Description Language API and Qiskit integrations. Access is provided through the Leap quantum cloud service. D-Wave describes the beta as being offered in advance of general availability, and the initial cohort is limited to selected commercial and research organizations rather than the broader developer community.
The modeled device is D-Wave's dual-rail superconducting cavity-qubit architecture. In this design, hardware-level detection is intended to identify primary photon-loss events and convert them into erasures with known spacetime locations. An erasure is different from an unknown error: the system records where and when the loss occurred, giving a quantum error-correction routine information that would otherwise have to be inferred.
That distinction is central to erasure-based correction. If a decoder knows the location of a damaged quantum state, it can use a different set of constraints from those applied to an error whose location is unknown. D-Wave presents this detection capability as a route toward more efficient quantum correction with lower hardware overhead as systems scale, but the simulator does not establish that such savings have been achieved in a complete processor.
The underlying entangling-gate mechanism was validated in peer-reviewed research published in Nature research, where the reported work demonstrated fast and high-fidelity two-qubit operations that preserved erasure-tracking signatures. That result is relevant to the architecture's physical motivation, but it should not be conflated with the present software beta: a demonstrated gate mechanism, an error-emulation environment and a fault-tolerant logical processor are separate engineering milestones. The broader quantum-control questions also sit within the research landscape studied at institutions such as MIT.
The numerical scope is specific. The beta environment supports circuits of up to 21 qubits and provides two execution modes; the available documentation does not report gate fidelities, coherence times, logical error rates, circuit depths or operating temperatures for the simulator or a deployed processor. Those omissions prevent a direct comparison with a functioning quantum computer.
BBVA and FirstQFM are among the initial commercial participants. Florida Atlantic University and the Jülich Supercomputing Centre are also taking part. Their stated tasks include evaluating mid-circuit error detection, testing real-time classical feedback and developing practical design rules for quantum machine-learning algorithms under physical hardware noise constraints.
Mid-circuit detection is central to the experiment because a useful error-aware system must do more than identify a problem after a computation has finished. It must register the event during execution and route that information into classical control and subsequent quantum operations. The beta can therefore expose software and control requirements that an ideal simulator would hide, although it cannot reproduce every calibration drift, hardware defect or environmental disturbance of a physical device.
The distinction between an announced pathway and a demonstrated capability also matters across the sector, as shown by earlier quantum coverage. Here, D-Wave is offering a concrete software environment for testing a defined architecture, not claiming that the beta itself delivers logical qubits or fault-tolerant computation.
The simulator's strongest contribution is methodological. It gives researchers a controlled place to compare ideal circuits with stochastic hardware emulation and to examine the feedback required when erasures are detected. That can improve circuit design and error-correction studies, especially for quantum machine learning where noise assumptions can change the behavior of an algorithm.
It does not answer the harder engineering questions. The available documentation provides no result showing that a logical error rate falls as the code grows, no demonstration of a complete error-corrected algorithm and no independent benchmark against a classical workflow. It also does not establish that the simulated architecture can be manufactured with stable performance, operated reliably at scale or integrated into a commercially useful processor.
D-Wave's beta is therefore best understood as an error-modeling and control testbed rather than a claim of computational superiority. The important advance is that users can work with erasure-aware programming before physical deployments; the unresolved issue is whether the same detection, feedback and correction assumptions survive contact with real hardware. Physical qubits are individual controllable systems, while logical qubits encode information across multiple physical resources to manage errors, and this 21-qubit simulator should not be mistaken for a 21-logical-qubit machine. That boundary is precisely why the program matters: it addresses a real systems problem without yet proving that the proposed solution is scalable or useful outside the simulated environment.
