HRL Laboratories has demonstrated an 18-qubit silicon spin quantum processor operating with a cryogenic CMOS controller, eliminating real-time room-temperature control and addressing key wiring and thermal bottlenecks in quantum hardware
HRL Laboratories has reported the experimental operation of an 18-qubit silicon spin quantum processing unit (QPU) that runs autonomously under the control of a custom cryogenic CMOS chip, according to a peer-reviewed study published in Nature. The demonstration replaces the conventional approach of routing hundreds of control signals from room-temperature electronics with a single integrated controller operating at 4 kelvins inside the cryostat. This architecture is designed to address two of the most persistent engineering challenges in scaling quantum processors: the physical complexity of wiring and the thermal load imposed by room-temperature control electronics.
Integrated Cryogenic Control
The HRL system integrates a 70-million-transistor, 130-nanometer RF-CMOS controller chip within the cryogenic environment, directly managing all qubit operations. The controller delivers 150 time-varying control waveforms to the mixing chamber, with a total power draw below 3.5 watts and less than 10 microwatts of thermal load reaching the sub-kelvin stage. This configuration maintains the electron temperature of the qubits at 150 millikelvin, a regime necessary for reliable spin qubit operation. The physical qubits are realized as exchange-only spin qubits in a 54-quantum-dot array fabricated on 200-millimeter isotopically enriched silicon-germanium wafers, with up to 18 qubits configured for active use.
Benchmarking and Error Rates
System benchmarks reported in the study show a significant reduction in error rates compared to previous exchange-only silicon spin qubit demonstrations. The QPU achieved average single-qubit gate errors of 1.7 × 10-4 and CNOT entangling gate errors of 3.5 × 10-3, with the lowest reproducible two-qubit gate errors reaching 9 × 10-4. Device charge noise, a major source of decoherence and gate error in semiconductor qubits, was reduced by an order of magnitude relative to earlier gate electrode designs. This enabled sub-microsecond gate execution and reduced the absolute gate error contribution from charge noise to 0.02%.
Error Detection and Logical Codes
To evaluate the system's capacity for error correction, the team implemented autonomous syndrome extraction routines for distance-3 and distance-5 repetition codes, incorporating real-time leakage-reduction units to suppress state leakage outside the computational subspace. The distance-5 code achieved an error-suppression scaling factor of Λ5/3 = 4.7, indicating improved logical performance as code distance increased. Additionally, a $[[4,2,2]]$ quantum error-detection code was executed across six physical qubits, with post-selection on error-detecting syndrome measurements sustaining two-logical-qubit state fidelity at 95% over three consecutive rounds. These results demonstrate the integration of error-detection protocols within a fully cryogenic control stack, but do not yet constitute full fault-tolerant quantum computation.
Manufacturing and Industry Context
The QPU, control logic, and high-density superconducting interconnects were all fabricated using standard commercial semiconductor processes, and the system was operated within a single commercial cryostat. This approach is intended to provide a manufacturing blueprint for scaling silicon spin quantum processors beyond laboratory prototypes. The demonstration arrives as IBM moves to finalize its acquisition of HRL Laboratories, a development that may influence the integration of silicon spin and cryogenic CMOS technologies into IBM's broader quantum hardware roadmap. For additional context on the strategic implications of this acquisition, see Science Report's coverage of IBM's plans to combine HRL's silicon-spin expertise with its superconducting quantum hardware program at this related article.
Quantum error correction is a set of techniques that encode logical qubits across multiple physical qubits to detect and correct errors arising from decoherence, control imperfections, and environmental noise. In practice, error correction requires not only high-fidelity gates and measurements but also the ability to extract error syndromes and apply corrections in real time, ideally without introducing additional errors or excessive latency. The distinction between error detection and full error correction is critical: while error-detection codes can identify certain errors and allow for post-selection, full fault tolerance requires that logical error rates decrease as code size increases and that all operations-including gates, measurements, and corrections-are protected against error propagation. Achieving this in hardware remains a central challenge for all quantum computing platforms.
