Quobly and SiPearl will study how an 80-core European ARM processor could interface with a silicon-spin QPU. The MoU targets hybrid HPC systems but does not yet demonstrate a working quantum integration or quantum advantage.
Europe's bid for sovereign quantum-computing hardware has moved from separate components toward a proposed system architecture. French silicon-spin-qubit developer Quobly and European high-performance-computing processor designer SiPearl signed a non-exclusive Memorandum of Understanding on 9 October 2026 to assess whether SiPearl's 80-core ARM-based Rhea1 CPU can work at system level with Quobly's silicon QPU hardware. The agreement is a feasibility study, not evidence of a completed integration or demonstrated quantum advantage.
The first phase will examine interfaces between the Rhea1 CPU, SiPearl's Seine reference server, Quobly's QPU control stack, and the cryogenic electronics platform needed to operate its quantum hardware. An independent French account identifies the Quobly Alloy product line as the reference quantum system for this initial technical assessment.
The intended result is a hybrid CPU-QPU design in which conventional computing resources handle tasks around a quantum coprocessor. That could include workload orchestration, calibration, measurement processing, and control, but the announcement does not report a working hybrid application, a measured quantum speedup, or a useful computation completed on the combined system.
That distinction matters. A host processor connected to quantum hardware is not automatically a quantum computer with practical advantage. The connection must support reliable state preparation, gate control, readout, data movement, calibration, and software coordination under the constraints imposed by a cryogenic device. In practice, the classical controller may also have to react to measurement results with sufficiently low latency while keeping heat dissipation compatible with the cryogenic stages.
SiPearl's Rhea1 uses 80 Arm Neoverse V1 cores, and its commercial release is expected by the end of 2026. The processor is also planned for JUPITER, a European exascale-class supercomputer designed to perform on the order of 1018 operations per second. That planned HPC context explains why the partnership is focused on system architecture: a QPU would operate as an accelerator within a much larger classical computing environment rather than as a stand-alone replacement for a supercomputer.
Quobly's approach uses silicon spin processors manufactured with semiconductor very-large-scale integration techniques. The company says its design places quantum-dot arrays alongside control circuitry on STMicroelectronics' 300mm FD-SOI manufacturing platform. In principle, that offers a route to treating parts of a quantum processor more like an advanced semiconductor system than a collection of individually assembled laboratory devices.
Silicon spin qubits encode information in the spin states of carriers confined in semiconductor structures. Isotopic purification to silicon-28 can reduce the concentration of silicon-29 nuclei, whose spins contribute to the surrounding magnetic environment; however, material purity alone does not determine processor performance. Interface defects, charge noise, gate control, readout fidelity, wiring, packaging, and thermal management all remain relevant engineering variables.
The announcement provides no qubit count, gate fidelity, readout fidelity, coherence time, operating temperature, device yield, or error rate for the QPU. It therefore establishes an engineering study around a proposed hardware stack, not a measured demonstration of quantum performance. No comparison with a classical workload is reported either.
The material supply chain is part of the same strategy. Quobly has identified isotopically purified silicon-28 as an industrial input for its processors, while its control platform is intended to connect the quantum-dot hardware with cryogenic electronics and a conventional host system. The central scientific question is whether semiconductor-scale manufacturing can preserve sufficiently uniform quantum behavior while also accommodating the dense control infrastructure required by a useful device.
The partnership follows Quobly's €115 million Series A financing round completed in June 2026. Bpifrance, STMicroelectronics, and SEALSQ led that round, according to the supplied announcement, which also links the company's hardware plans to an industrial silicon-28 supply chain.
Quobly says it plans to provide cloud access to its first systems from the end of 2026 and aims to reach one million qubits by 2032. These are company road-map targets, not demonstrated results. The partnership also connects to European industrial policy: Quobly and SiPearl intend to coordinate submissions to European tenders, including quantum competitions associated with the European Union's Chips Joint Undertaking.
The partners intend to align their commercial roadmaps and submit joint proposals to European funding programs. Planned applications are not evidence that the companies have already secured a grant or deployed a sovereign HPC-quantum installation. The arrangement instead fits a wider European hardware logic: keep the processor, semiconductor manufacturing route, quantum device, and server architecture within a regional industrial network.
Readers tracking how software and classical infrastructure constrain quantum systems can also consult this earlier hardware analysis, although Quobly and SiPearl are addressing integration rather than fault-tolerant compilation.
The difficult work now lies below the level of corporate roadmaps. A useful CPU-QPU system would need stable interfaces between room-temperature computing and cryogenic control, a practical division of workloads, synchronized measurement, and software capable of managing calibration and experimental data. The announcement does not yet disclose how those functions will be implemented or what performance target would define success.
Quantum error correction adds another layer of complexity. A physical qubit is an individual quantum device whose state must be prepared, controlled, and measured; a logical qubit encodes information across multiple physical qubits so that errors can be detected and corrected. Experiments reported in Nature's surface-code study illustrate why scaling, error suppression, and repeated syndrome measurements matter more than a raw physical-qubit count. Nothing in the Quobly-SiPearl announcement reports logical qubits, a fault-tolerant cycle, or an error-correction demonstration.
Quobly's silicon approach may reduce some manufacturing barriers if quantum-dot arrays and control circuitry can be produced with repeatable semiconductor processes. But a 300mm platform alone does not establish reproducible quantum-device performance. Variability, wiring density, control noise, readout, thermal load, packaging, and device-to-device consistency remain system questions that the feasibility study is meant to investigate.
The partnership is therefore significant as an architectural commitment rather than a quantum breakthrough. It places a European ARM CPU and a silicon-spin QPU in the same engineering plan while leaving the central evidence still to be produced: a demonstrated interface, measured quantum operation, and a workload whose full-system performance justifies the added complexity.
In this context, the classical processor would coordinate tasks analogous to those handled in large-scale computing facilities such as systems associated with CERN and MIT research laboratories, while the QPU would serve a specialized accelerator role. That analogy should not be mistaken for evidence of a deployed CERN- or MIT-integrated quantum system; it simply highlights the established division between general-purpose orchestration and specialized scientific accelerators.
The credible conclusion is narrower but important: Europe is testing whether sovereign classical and quantum semiconductor infrastructure can be designed as one stack. The value of that plan will depend on measured integration, reproducible device parameters, transparent workload benchmarks, and eventually evidence that error-corrected performance offers a meaningful benefit over classical alternatives.
