A team from the University of Southern California and Quantum Elements has experimentally tested surface code error suppression on IBM's 156-qubit heavy-hex superconducting processors, challenging assumptions about lattice geometry and quantum error correction.
Quantum error correction is widely seen as the bridge between today's noisy quantum devices and future fault-tolerant quantum computers. Most experiments so far have used ideal square-lattice connectivity, leaving open the question of whether real processor layouts can support scalable error suppression. Researchers from the University of Southern California (USC) and Quantum Elements have now reported subthreshold surface code scaling on IBM's heavy-hex superconducting quantum processors, directly addressing this issue. Their results, published in Nature Communications, offer new data for the quantum computing community.
IBM's heavy-hex architecture arranges superconducting qubits on a honeycomb lattice, not the square grid usually assumed in surface code theory. This setup introduces routing delays and idle periods, which can lead to non-Markovian dephasing and coherent ZZ crosstalk-both types of noise that degrade quantum information. The experiment used IBM Heron-generation processors with 156 physical qubits, making use of the largest heavy-hex connectivity available for this device class. The heavy-hex topology is sparser than a square lattice, so adapting surface code protocols was a central challenge for the USC and Quantum Elements team.
To make the surface code work on this geometry, the team used a depth-minimizing SWAP-based "fold-unfold" embedding, with bridge ancilla qubits to maintain logical connections. They paired this with robust dynamical decoupling (DD) protocols to suppress idle-time noise and reduce hardware-induced crosstalk. The software layer relied on Quantum Elements' Orbit Qiskit Function, which integrated hardware-aware control sequences into the experiment. Daniel Lidar, a lead researcher, noted that only by using these advanced DD techniques could the team demonstrate the expected improvements in error suppression, highlighting the need for hardware-software co-design in quantum error correction research.
The researchers ran surface code circuits at increasing code distances, starting from d = 3 (37 qubits) and extending to anisotropic configurations (3,5) and (5,3) with 65 qubits. They performed up to 10 quantum error correction (QEC) cycles, with circuit depths over 140 layers and a total of 2,200 entangling gates. The main question was whether logical error rates per cycle would drop as code distance increased, even with non-square connectivity and extra noise. These benchmarks follow best practices from institutions like MIT and CERN, which stress rigorous statistical validation in quantum hardware experiments.
To measure logical error rates accurately, the team introduced a SPAM-aware entanglement fidelity (EF) metric, which accounts for state preparation and measurement (SPAM) errors without assuming stationary noise. This gave a more precise view of error suppression per QEC cycle. The results showed that, with advanced DD and careful embedding, the heavy-hex architecture can support distance-dependent error suppression-a key requirement for scalable quantum error correction. The study's methods and statistical analysis were peer-reviewed, with confidence intervals reported for logical error rates at each code distance.
A major challenge in this experiment was the buildup of idle noise and crosstalk during routing and SWAP operations. Without robust DD, these effects can mimic subthreshold scaling, leading to misleading claims of error suppression. The study warns that unmitigated idle noise can produce results that look like error suppression but are not genuine. By integrating gap-aware DD into the control stack, the researchers showed that real error suppression is possible, but only with mitigation strategies tailored to the processor's connectivity and noise profile. This approach matches recommendations from the Max Planck Society and other research organizations, which call for comprehensive noise modeling in quantum device benchmarking.
This work builds on earlier simulation efforts by the same group. In June 2026, USC and Quantum Elements published a Quantum Monte Carlo (QMC) method for simulating noisy surface code circuits up to 97 qubits, providing a classical foundation for hardware-calibrated QEC design. For readers interested in the broader context of quantum software and error correction, an earlier breakdown covers modular approaches to quantum circuit complexity.
While this demonstration shows that heavy-hex processors can support subthreshold surface code scaling, several engineering hurdles remain. The experiment was limited to 10 QEC cycles and code distances set by the available qubit count and connectivity. Logical error rates were measured per cycle, but total logical lifetime and the feasibility of real-time decoding were not addressed. The results do not establish full fault tolerance or practical quantum memory, but they do provide experimental evidence that non-square architectures are not automatically excluded from scalable error correction-if noise mitigation is integrated at the hardware-control level.
For the field, these results move error correction benchmarks closer to the realities of actual devices, rather than idealized models. The use of SPAM-aware fidelity metrics and the explicit warning against misleading scaling claims set a higher bar for future experiments. As quantum hardware evolves, adapting error correction protocols to different architectures will be essential for progress toward fault-tolerant computation. The evidence here is clear: error suppression is possible on heavy-hex processors, but only through careful co-design of hardware, control, and software.
Quantum error correction encodes quantum information across multiple physical qubits so that errors from noise, decoherence, or imperfect control can be detected and corrected without directly measuring the encoded state. The surface code is a leading error-correcting code that arranges qubits in a two-dimensional lattice, using local measurements to detect errors. The "code distance" is the minimum number of physical errors needed to corrupt the logical information; increasing code distance should, in principle, reduce the logical error rate if the physical error rate is below a certain threshold. Achieving subthreshold scaling-where logical errors decrease as the code grows-is a necessary but not sufficient step toward practical fault-tolerant quantum computing. Real-world architectures, noise sources, and control limitations mean that every experiment must be checked for genuine error suppression, not just apparent improvements caused by unmitigated noise or measurement artifacts.
