Dell and Diraq Place Silicon Qubits Beside HPC Servers

A Dell high-performance computing cluster is now operating inside Diraq's Sydney laboratory beside the company's silicon spin-qubit hardware. The physical arrangement is the central result: instead of treating the quantum processor as a remote accelerator, the companies are testing whether classical computing and a quantum processing unit can exchange control data with sufficiently low delay for hybrid workflows. Diraq describes the installation as a practical integration testbed focused on stable connectivity, baseline latency validation and simple test circuits.

The co-located hardware
Diraq develops silicon spin qubits while Dell Technologies supplies enterprise computing infrastructure. Their testbed places a small Dell cluster next to Diraq's silicon QPU and connects the systems through high-speed networking. The companies say this arrangement is intended to reduce the delay between quantum measurements and classical decisions during a computation, although no measured latency has been publicly reported.
That distinction matters because a QPU does not operate as an independent replacement for an HPC system. Classical processors prepare control signals, process measurements, update calibration parameters and can direct subsequent quantum operations. When feedback steps take too long, the quantum device may spend more time waiting and operating conditions may change before the next instruction is ready. The same systems challenge appears in other experimental fields, where instruments and control computers must coordinate within tightly defined timing windows; it is an engineering issue rather than evidence of quantum advantage.
The announcement does not provide a qubit count, gate fidelity, readout fidelity, coherence time, operating temperature or measured latency for the Dell deployment. It therefore establishes a deployment and integration testbed rather than a quantified demonstration of computational superiority. The Diraq laboratory announcement presents the early work as infrastructure validation and workflow testing.

Control loops under test
The initial work centers on hybrid workflow orchestration. Classical software is being adapted to support real-time qubit calibration, tuning and near-term quantum error-correction protocols. In practical terms, the cluster processes measurement information and feeds control decisions back to the QPU without requiring a separate bespoke computing model for every operating loop.
Calibration is not a minor software task in a quantum processor. Control parameters can drift, measurement errors can distort the inferred state and interactions between neighboring qubits can introduce crosstalk. Automated routines may help keep a device within its intended operating range, but the available announcement does not report calibration accuracy, execution time, statistical uncertainty or whether the procedure improves multi-qubit performance. A rigorous evaluation would normally specify repeated trials, device conditions, confidence intervals and a comparison with an established calibration baseline.
The same caution applies to the reference to quantum error correction. The collaboration describes near-term QEC protocols and loop execution, but it does not identify a code, the number of physical or logical qubits, a decoder, a logical error rate or a successful fault-tolerant computation. Error correction is a family of techniques for detecting and correcting faults; mentioning an automated QEC loop is not evidence that errors have been eliminated or that a protected logical processor has been built. The distinction is consistent with how institutions such as MIT and CERN separate control-system demonstrations from validated performance claims in large experimental platforms.

Silicon meets enterprise computing
The partnership is built around a potentially important architectural compatibility. Diraq's silicon spin-qubit processors are described as being fabricated through standard CMOS semiconductor processes, while Dell's systems are designed for conventional data-center environments. Silicon spin qubits exploit charge and spin behavior in semiconductor devices, and CMOS compatibility is presented by Diraq as a route toward manufacturing scalability and closer integration with established electronics. However, compatibility at the materials and process level does not by itself establish high-yield manufacturing, uniform device performance or reliable large-scale operation.
Diraq and Dell are evaluating hybrid applications in large-scale optimization, supply-chain logistics, financial portfolio modeling and AI-assisted molecular drug discovery. These are proposed application areas rather than reported demonstrations. No benchmark, classical baseline, runtime, energy comparison or useful output is supplied for any of them, so the announcement cannot support a claim that the QPU currently improves one of these workflows. As in computational studies reported in journals such as Nature, a credible application claim would require a defined problem instance, reproducible methodology and quantitative comparison with strong classical alternatives.
The stated long-range objective is scaling to millions of qubits on a chip. That is an architectural target, not a demonstrated device result. Moving from a silicon process to a useful processor would require reproducible fabrication, uniform qubit control, manageable wiring, stable calibration, low crosstalk, effective readout and an error-correction system whose classical decoding can keep pace with the hardware. The difficulty is not only the number of qubits but also the quality and coordination of every element in the control stack.

A separate logical-qubit milestone
A recent Diraq-related technical result should be kept separate from the Dell co-location experiment. Iceberg Quantum has described its Pinnacle architecture on Diraq hardware as targeting 1,000 logical qubits from 150,000 physical qubits. That figure is an architecture-level target, not a reported count of logical qubits operating in the Sydney Dell deployment. In a separate announcement, NVIDIA said Diraq used NVIDIA Ising to calibrate its silicon-based qubit processor. These developments show activity around software, calibration and fault-tolerant architecture, but they do not supply the missing performance measurements for the co-located HPC testbed.

What the testbed shows
The strongest evidence in the collaboration is physical co-location: Dell has deployed a server cluster in Diraq's Sydney laboratory beside the silicon quantum hardware. The remaining evidence describes active technical work, not an independently verified performance result. The available material includes no peer-reviewed paper, independent replication or numerical benchmark that would allow readers to compare this arrangement with a conventional remote or locally integrated control system. NASA and other major research organizations routinely distinguish infrastructure readiness from validated instrument performance; the same standard is appropriate here.
The infrastructure question is part of a wider financing and commercialization story in quantum technology. A separate earlier funding report described Canada's BDC directing $1 billion toward quantum and deep-tech startups, but capital and computing infrastructure are not substitutes for demonstrated qubit performance.
Andrew Dzurak and John Roese lead the collaboration as Diraq's founder and CEO and Dell's global CTO, respectively. Dzurak has described the broader goal as creating integrated systems in which classical AI and CPUs perform large-scale computation while the QPU is reserved for specific difficult subproblems. The Sydney installation is an engineering test of that division of labor, not a claim that quantum processors have already outperformed classical machines.
Physical and logical qubits are central to reading the claim correctly. A physical qubit is an individual controllable quantum system; a logical qubit encodes information across multiple physical qubits so that errors can be detected and, in suitable architectures, corrected. A server cluster beside a QPU can accelerate control and analysis, but it does not convert physical qubits into logical ones or make a processor fault tolerant.
The collaboration is therefore best understood as a credible integration step addressing a real systems problem: fast coordination between quantum measurements and classical control. Its eventual scientific importance will depend on measurements that have not yet been disclosed, including end-to-end latency distributions, calibration stability, control-loop success rates, error correlations and comparisons with remote orchestration. Until those data are reported, the Sydney installation is promising infrastructure rather than proof of a commercially useful quantum computer.