D-Wave Quantum Inc. has experimentally demonstrated a fast, high-fidelity two-qubit entangling gate for superconducting dual-rail cavity qubits, addressing key error sources and hardware overhead in quantum error correction architectures
D-Wave Quantum Inc. has reported the experimental realization of a two-qubit entangling gate for superconducting dual-rail cavity qubits, as detailed in a peer-reviewed study published in Nature. The work targets a central challenge in quantum computing: reducing the physical qubit overhead required for fault-tolerant operation by making dominant error processes detectable and correctable at the hardware level.
Dual-Rail Cavity Qubit Architecture
The experiment used dual-rail cavity qubits, where quantum information is encoded in the presence or absence of photons across two superconducting microwave cavities. This approach allows photon loss-the main error channel in such systems-to be converted into erasure errors that can be detected at known spacetime locations. The architecture is designed to suppress bit-flip errors and maintain a strong noise bias, which is advantageous for surface-code quantum error correction.
Gate Implementation and Performance
The team implemented a controlled-phase (CZ) gate using a Swap-Wait-Swap (SWS) protocol. In this scheme, a photon from one cavity is temporarily swapped into a tunable transmon coupler, where it experiences a strong dispersive interaction with a second cavity before being swapped back. The gate operated at a speed of approximately 500 nanoseconds. Experimental results showed a physical gate fidelity of about 99.9%, with an erasure rate near 0.5% per gate and post-selected residual Pauli errors below 0.1%. Bit-flip errors were suppressed to the 10-6 level, while dephasing errors remained the dominant residual noise source. The architecture also demonstrated benign leakage propagation: photon loss to the vacuum state deactivates the interaction, allowing erasure checks to be deferred without increasing correlated error risk.
Error Correction and Scalability
Numerical simulations based on the measured parameters indicate that the dual-rail architecture can achieve an error reduction factor (Λ) of 10 for each increment in surface-code distance. This means that logical error rates decrease by a factor of 10 with each additional layer of error correction, significantly reducing the number of physical qubits required compared to standard transmon-based or planar surface-code systems. The hardware-level detection of erasure errors simplifies classical decoding and supports the construction of logical qubits with lower overhead.
Roadmap and Remaining Challenges
D-Wave's published roadmap projects a sequence of increasingly capable systems, beginning with a 17-physical-qubit device (DR17) targeting a twofold logical error reduction by 2026, followed by a 49-qubit system (DR49) aiming for a 20-fold reduction in 2027, and a 181-qubit system (DR181) with a projected 2,000-fold error suppression by 2028. The company plans to scale to a 10-logical-qubit system by 2030 and a 100-logical-qubit system by 2032, with the goal of supporting quantum chemistry, materials science, and quantum AI applications. However, these targets remain projections, and the transition from laboratory demonstration to robust, large-scale fault-tolerant operation will require further advances in device yield, calibration stability, and system integration. The platform is expected to be accessible via D-Wave's Leap(TM) quantum cloud service, with real-time quantum-classical control and support for the Quantum Circuit Description Language (QCDL).
While D-Wave's approach focuses on hardware-detectable erasure errors and noise bias, other quantum hardware developers are pursuing alternative strategies for error correction and logical qubit construction. For example, recent work by IBM and collaborators has explored verified quantum tasks beyond classical supercomputer reach, as discussed in this related report. The field continues to evaluate which architectures and error models will prove most practical for scalable quantum computing.
Quantum error correction is essential for building reliable quantum computers. Physical qubits are prone to errors from decoherence, control imperfections, and environmental noise. Logical qubits encode information across multiple physical qubits using error-correcting codes, allowing errors to be detected and corrected without measuring the encoded quantum information directly. Surface codes are a leading approach, but require high-fidelity gates, low error rates, and efficient error detection. Erasure errors-where the location and time of an error are known-are easier to correct than random errors, reducing the overhead for fault-tolerant operation. The ability to convert dominant error processes into erasures at the hardware level is a significant step toward practical quantum error correction, but scaling these techniques to large, stable systems remains a major engineering challenge.
